This invention relates generally to semiconductor devices, and more particularly to a clock control circuit for controlling internal clock signals of semiconductor devices, especially non-volatile semiconductor memory devices such as flash memory devices.
Generally, a flash memory device comprises an address sequencer, row and column decoders, sense amplifiers, write amplifiers, and a memory cell array. An example of a flash memory device is described in U.S. Pat. No. 5,490,107, the disclosure of which is herein incorporated by reference. The memory cell array contains a plurality of memory cells arranged in rows and columns. Each memory cell is capable of holding a single bit of information. A column of memory cells in the memory cell array is commonly coupled to a bit line. The column decoder along with the address sequencer selects a bit line. Similarly, the memory cells arranged in a row of the memory cell array are commonly coupled to a word line. The row decoder and address sequencer selects a word line. Together the row and column decoders and the address sequencer selects an individual memory cell or a group of memory cells.
The memory cells in the memory cell array of a flash memory device are generally grouped into sub-arrays called memory cell blocks. Each memory cell block is coupled to a sense amplifier and a write amplifier. The write amplifier (W/A) applies a set of predetermined voltages to store information in the selected memory cells. This action is referred to as a program or write operation. Similarly, a set of predetermined voltages applied to the selected memory cells allows information to be discriminated and retrieved by the sense amplifier (S/A). This action is referred to as a read operation.
The speed of read and write operations is often increased in order to realize higher performance flash memory devices. One such method to increase the speed of read operations is synchronization. By synchronizing the read operations to an external clock, the speed of the read operations is improved. However, under certain conditions, a specific read operation may take longer to perform than other read operations, and thus an asynchronous condition may occur.
For example, when a word line switch occurs, i.e. when reading the first memory cell along a word line after reading the last memory cell along the previous word line in a memory cell, a delay is often experienced. This delay is often greater than one clock period of the external clock and thus disrupts the synchronization of the read operation to the external clock. As a result, an error occurs such that incorrect data is read from the selected memory cell.